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PACE1750AE SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic Form-Fit-Functionally Compatible with the P1750A DAIS Instruction Mix Execution Performance Including Floating Point Arithmetic 1.8 MIPS at 20 MHz 2.7 MIPS at 30 MHz 3.6 MIPS at 40 MHz Conventional Integer Processing Mix Performance 5.0 MIPS at 40 MHz Power BIF Instructions Allow for High Throughput Implementations of Transcedental Functions, Navigational Algorithms and DSP Functions - Inner Dot Product Instruction for 3X3, 16 Bit Registers in 150ns (2 clocks per Multiply/ Accumulate step) with 32 Bits Result - Multiply/Accumulate Instructions for 32 Bit Registers is 200ns at 40MHz (8 clocks), with 48 Bit Result - Parameteric Memory Inner-Dot Products for Matrix Computations up to 64K - Fast Polynomial expansion algorithms - Fast context switching with Instruction to block move up to 16 new mapping memory page registers 20, 30, and 40 MHz Operation over the Military Temperature Range Extensive Error and Fault Management and Interrupt Capability 26 User Accessible Registers Single 5V 10% Power Supply Power Dissipation over Military Temperature Range <0.5 watts at 20 & 30 MHz <1.0 watts at 40 MHz TTL Signal Level Compatible Inputs and Outputs Multiprocessor and Co-processor Capability Two programmable Timers Available in: - 64-Pin Top Brazed DIP - 68-Pin Pin Grid Array (PGA) - 68-Lead Quad Pack (Leaded Chip Carrier)
GENERAL DESCRIPTION
The PACE1750AE is a general purpose, single chip, 16bit CMOS microprocessor designed for high performance floating point and integer arithmetic, with extensive real time environment support. It offers a variety of data types, including bits, bytes, 16-bit and 32-bit integers, and 32-bit and 48-bit floating point numbers. It provides 13 addressing modes, including direct, indirect, indexed, based, based indexed and immediate long and short, and it can access 2 MWords of segmented memory space (64 KWords segments). The PACE1750AE offers a well-rounded instruction set with 130 instruction types, including a comprehensive integer, floating point, integer-to-floating point and floating point-to-integer set, a variety of stack manipulation instructions, high level language support instructions such as Compare Between Bounds and Loop Control Instructions. It also offers some unique instructions such as vectored l/O, supports executive and user modes, and provides an escape mechanism which allows user-defined instructions, using a coprocessor. The chip includes an array of real time application support resources, such as 2 programmable timers, a complete interrupt controller supporting 16 levels of prioritized internal and external interrupts, and a faults and exceptions handler controlling internally and externally generated faults. The microprocessor achieves very high throughput of 3.6 MIPS for a standard real time integer/floating point instruction mix at a 40 MHz clock. It executes integer Add in 0.1 s, integer Multiply in 0.1 s, Floating Point Add in 0.45 s, and Floating Point Multiply in 0.225 s, for register operands at a 40 MHz clock speed. The PACE1750AE uses a single multiplexed 16-bit parallel bus. Status signals are provided to determine whether the processor is in the memory or I/O bus cycle, reading and writing, and whether the bus cycle is for data or instructions.
Document # MICRO-2 REV G Revised October 2005
PACE1750AE
DIFFERENCES BETWEEN THE PACE1750A AND PACE1750AE
The PACE1750AE achieves a 41% boost in performance (in clock cycles) over the PACE1750A. This reduction in clocks per instruction is because of three architectural enhancements: 1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array. 2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU's peripheral chips). 3) Branch calculation logic. The table below shows how the MAC improves all multiply operations -- both integer and floating point -- by 477% to 760%. PACE1750AE Instruction Integer Add/Sub Double Precision Integer Add/Sub Integer Multiply Double Precision Integer Add/Sub Floating Add/Sub Extended Floating Add/Sub Floating Multiply Extended Floating Point Multiply Branch (Taken) Branch (Not Taken) Flt'g' Point Polynomial Step (Mul+Add/Sub) Ext Flt'g' Point Polynomial Step (Mul/Sub) DAIS Mix (MIPS) Clocks 4 6 4 9 18 34 9 17 8 4 27 51 -- Execution Time (40 MHz) 100ns 150ns 100ns 225ns 450ns 850ns 225ns 425ns 200ns 100ns 675ns 1275ns 3.56 PACE1750A Clocks 4 9 23 69 28 51 43 96 12 4 71 147 -- Execution Gain Time (40 MHz) #Clocks (%) 100ns 225ns 575ns 1725ns 700ns 1225ns 1075ns 2400ns 300ns 100ns 1775ns 3675ns 2.52 -- 50 575 760 55 50 477 564 50 -- 263 2400 41/59
PACE1750AE BUILT IN FUNCTIONS
A core set of additional instructions have been included in the PACE1750AE. These instructions utilize the Built ln Function (BlF) opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application areas such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BlFs and their execution times (N = the number of elements in the vector being processed). Instruction Memory Parametric Dot Product--Single Memory Parametric Dot Product--Double 3 x 3 Register Dot Product Double Precision Multiply Accumulate Polynomial Clear Accumulator Store Accumulator (32-Bit) Store Accumulator (48-Bit) Load Accumulator (32-Bit) Load Accumulator Long (48-Bit) Move MMU Page Block Load Timer A Reset Register Load Timer B Reset Register Mnemonic VDPS VDPD R3DP MACD POLY CLAC STA STAL LAC LACL MMPG LTAR LTBR Address Mode 4F3(RA) 4F1(RA) 4F03 4F02 4F06 4F00 4F08 4F04 4F05 4F07 4F0F 4F0D 4F0E Number of Clocks 10 + 8 * N 10+16 * N 6 8 7*N-2 4 7 11 9 9 16+8 * N 4 4 Privileged Notes Interruptable Interruptable
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PACE1750AE
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage Range Input Voltage Range -0.5V to 7.0V -0.5V to VCC + 0.5V Thermal resistance, junction-to-case (JC), Note 5: Cases X and T Cases Y and U Case Z 8C/W 5C/W 6C/W
Storage Temperature Range -65C to + 150C Input Current Range Voltage Applied to Inputs Current Applied to Outputs3 -30mA to +5mA -0.5V to VCC + 0.5V 150 mA
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range 4.5V to 5.5V Case Operating Temperature -55C to +125C Range
Maximum Power Dissipation2 1.5W Operating worst case power dissipation (outputs open), Note 4: Device type 05 (20 MHz) Device type 06 (30 MHz) Device type 07 (40 MHz) Lead Temperature Range (soldering 10 seconds) 0.4W at 20 MHz 0.5W at 30 MHz 0.6W at 40 MHz 300 C
NOTE 1: Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. NOTE 2: Must withstand the added power dissipation due to short circuit test e.g., IOS NOTE 3: Duration one second or less. NOTE 4: Device Type Definitions from 5962-87665 SMD: Device Type 05: 20 MHz Device Type 06: 30 MHz Device Type 07: 40 MHz NOTE 5: Case Definitions from 5962-87665 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array
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PACE1750AE
DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions)
Symbol VIH VIL VCD VOH Parameter Input HIGH Level Voltage Input LOW Level Voltage2 Input Clamp Diode Voltage Output HIGH Level Voltage 2.4 VCC - 0.2 VOL Output LOW Level Voltage Input HIGH Level Current, IIH1 except IB0 - IB15, BUS BUSY, BUS LOCK Input HIGH Level Current, IB0 - IB15, BUS BUSY, BUS LOCK Input LOW Level Current, except IB0 - IB15, BUS BUSY, BUS LOCK Input LOW Level Current, IB0 - IB15, BUS BUSY, BUS LOCK Output Three-State Current Output Three-State Current Quiescent Power Supply Current (CMOS Input Levels) Quiescent Power Supply ICCQT Current (TTL Input Levels) Dynamic Power ICCD Supply Current 20 MHz 30 MHz 40 MHz IOS CIN COUT CI/O Output Short Circuit Current3 Input Capacitance Output Capacitance Bi-directional Capacitance -25 10 15 15 50 70 85 100 mA mA mA mA mA pF pF pF 10 A VIN = VCC, VCC = 5.5V 0.5 0.2 Min 2.0 -0.5 Max VCC + 0.5 0.8 -1.2 Unit V V V V V V V VCC = 4.5V, IIN = -18mA VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V IOH = -8.0mA IOH = -300A IOL = 8.0mA IOL = 300A Conditions1
IIH2
50
A
VIN = VCC, VCC = 5.5V
IIL1
-10
A
VIN = GND, VCC = 5.5V
IIL2 IOZH IOZL ICCQC
-50 50 -50 20
A A A mA
VIN = GND, VCC = 5.5V VOUT = 2.4V, VCC = 5.5V VOUT = 0.5V, VCC = 5.5V VIN < 0.2V or < VCC - 0.2V, f = 0MHz, Outputs Open, VCC = 5.5V VIN < 3.4V, f = 0MHz, Outputs Open, VCC = 5.5V VIN = 0V to VCC, tr = tf = 2.5 ns, Outputs Open, VCC = 5.5V VOUT = GND, VCC = 5.5V
Notes 1. 4.5V VCC 5.5V, -55C TC +125C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = -3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time.
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PACE1750AE
SIGNAL PROPAGATION DELAYS
1,2
20 MHz Symbol Parameter BUS REQ BUS REQ BUS GNT setup BUS GNT hold BUS BUSY LOW BUS BUSY HIGH BUS BUSY setup BUS BUSY hold BUS LOCK LOW BUS LOCK HIGH BUS LOCK setup Min Max
30 MHz Min Max
40 MHz Min Max Unit
tC(BR)L tC(BR)H tBGV(C) tC(BG)X tC(BB)L tC(BB)H tBBV(C) tC(BB)X tC(BL)L tC(BL)H tBLV(C)
25 25 5 5 24 20 5 5 25 20 5 5 20 25 0 17 17 5 5 5 17 17 17 0 25 26 5 5 25 0 5 6 0 0 5 6 0 0 25 26 5 5 5 5 5 0 5 5 5 5 5 5
25 25 5 5 24 20 5 5 25 20 5 5 20 25 0 17 17 5 5 5 17 17 17 0 17 20 5 5 25 0 5 5 0
22 22
ns ns ns ns
20 15
ns ns ns ns
21 17
ns ns ns ns
tC(BL)X (IN) BUS LOCK hold tC(ST)V tC(ST)X tC(SA)H tC(SA)L tRAV(C) tC(RA)X tC(SDW)L tC(SD)H tSDRH(IBD)X
D/ I Status, AS0-AS3, AK0-AK3, M/ IO, R/ W M/ IO, R/ W, D/ I Status, AS0-AS3, AK0-AK3 STRBA HIGH STRBA LOW
20 20
ns ns ns
16 16
ns ns ns ns ns
tSAL(IBA)X Address hold from STRBA LOW
RDYA setup RDYA hold STRBD LOW write STRBD HIGH STRBD HIGH
14 14 14
ns ns ns ns ns ns ns ns
tFC(SDR)L STRBD LOW read tSDWH(IBD)X STRBD HIGH tSDL(SD)H STRBD write tRDV(C) tC(RD)X tC(IBA)V tFC(IBA)X tC(IBD)X tC(IBD)X
RDYD setup RDYD hold IB0-IB15 IB0-IB15
20
ns ns ns ns ns
tIBDRV(C) IB0-IB15 setup
IB0-IB15 hold (read) Data valid out (write)
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PACE1750AE
SIGNAL PROPAGATION DELAYS
1,2
(continued)
20 MHz 30 MHz Min Max 40 MHz Min Max Unit
Symbol
Parameter IB0-IB15 SNEW TRIGO RST
Min
Max
tFC(IBD)V tC(SNW) tFC(TGO) tC(DME) tFC(NPU) tC(ER) tRSTL(NPU) tREQV(C) tC(REQ)X tFV(BB)H tBBH(F)X tIRV(C) tC(IR)X
25 26 26 35 35 35 50 40 0 10 5 5 0 10 20 17 5 5 5 0 10 5 5 0 10 20
25 25 25 35 35 35 50 40 0 10 5 5 0 10 15 17 5 5
20 22 22 30 30 30 45 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRSTL(DMA ENL) DMA enable
DMA enable Normal power up Clock to major error unrecoverable RESET Console request Console request Level sensitive faults Level sensitive faults IOL1-2INT user interrupt (0-5) setup Power down interrupt level sensitive hold
tRSTL (tRSTH) Reset pulse width tC(XX)Z tf(F), t1(1) tr, tf
Clock to three-state Edge sensitiive pulse width Clock rise and fall
13 5
ns ns ns
Notes 1. 4.5V VCC 5.5V, -55C TC +125C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced. When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
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PACE1750AE
MINIMUM WRITE BUS CYCLE TIMING DIAGRAM
Note: All time measurements on active signals relate to the 1.5 volt level.
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PACE1750AE
MINIMUM READ BUS CYCLE TIMING DIAGRAM
Note: All time measurements on active signals relate to the 1.5 volt level.
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PACE1750AE
MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM
Note: All time measurements on active signals relate to the 1.5 volt level.
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PACE1750AE
TRIGO RST DISCRETE TIMING DIAGRAM
DMA EN DISCRETE TIMING DIAGRAM
NORMAL POWER UP DISCRETE TIMING DIAGRAM
XIO OPERATIONS
SNEW DISCRETE TIMING DIAGRAM
Note: All time measurements on active signals relate to the 1.5 volt level.
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PACE1750AE
EXTERNAL FAULTS AND INTERRUPTS TIMING DIAGRAM
Edge-sensitive interrupts and faults (SYSFLT0, SYSFLT1) min. pulse width Level-sensitive interrupts
Note: tC(IR)X max = 35 clocks
Level-sensitive faults
CON REQ
Note: All time measurements on active signals relate to the 1.5 volt level.
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PACE1750AE
BUS ACQUISITION
Note: A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is assserted and the BUS is not locked (BUS LOCK is high).
SWITCHING TIME TEST CIRCUITS
Standard Output (Non-Three-State) Three-State
Note: All time measurements on active signals relate to the 1.5 volt level.
Parameter tPLZ tPHZ tPXL tPXH
V0 3V 0V VCC/2 VCC/2
VMEA 0.5V VCC - 0.5V 1.5V 1.5V
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PACE1750AE
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS Mnemonic CPU CLK TIMER CLK Name CPU clock Timer clock Description A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty cycle. A 100 KHz input that, after synchronization with CPU CLK, provides the clock for timer A and timer B. If timers are used, the CPU CLK signal frequency must be > 300 KHz. An active low input that initializes the device. An active low input that initiates console operations after completion of the current instruction.
RESET CON REQ
Reset Console request
INTERRUPT INPUTS Mnemonic PWRDN INT Name Power down interrupt Description An interrupt request input that cannot be masked or disabled. This signal is active on the positive going edge or the high level, according to the interrupt mode bit in the configuration register. Interrupt request input signals that are active on the positive going edge edge or the high level, according to the interrupt mode bit in the configuration register. Active high interrupt request inputs that can be used to expand the number of user interrupts.
USR0INT USR5INT IOL1INT IOL2INT FAULTS Mnemonic MEM PRT ER
User interrupt
I/O level interrupts
Name Memory protect error
Description An active low input generated by the MMU or BPU, or both and sampled by the BUS BUSY signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus cycle). An active low input sampled by the BUS BUSY signal into bit 2 of the fault register.
MEM PAR ER EXT ADR ER SYSFLT0 SYSFLT1 ERROR CONTROL Mnemonic UNRCV ER MAJ ER
Memory parity error
External address error An active low input sampled by the BUS BUSY signal into the Fault register (bit 5 or 8), depending on the cycle (memory or I/O). System fault 0, System fault 1, Asynchronous, positive edge-sensitive inputs that set bit 7 (SYSFLT0) or bits 13 and 15 (SYSFLT1) in the Fault register.
Name Unrecoverable error Major error
Description An active high output that indicates the occurrence of an error classified as unrecoverable. An active high output that indicates the occurrence of an error classified as major.
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PACE1750AE
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL Mnemonic D/I Name Data or instruction Description An output signal that indicates whether the current bus cycle access is for Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not assigned to the CPU. This line can be used as an additional memory address bit for systems that require separate data and program memory. An output signal that indicates direction of data flow with respect to the current bus master. A HIGH indicates a read or input operation and a LOW indicates a write or output operation. The signal is three-state during bus cycles not assigned to the CPU. An output signal that indicates whether the current bus cycle is memory (HIGH) or I/O (LOW). This signal is three-state during bus cycles not assigned to the CPU. An active HIGH output that can be used to externally latch the memory or I/O address at the HIGH-to-LOW transition of the strobe. The signal is three-state during bus cycles not assigned to the CPU. An active HIGH input that can be used to extend the address phase of a bus cycle. When RDYA is not active, wait states are inserted by the device to accommodate slower memory or I/O devices. An active LOW output that can be used to strobe data in memory and XIO cycles. This signal is three-state during bus cycles not assigned to the CPU. An active HIGH input that extends the data phase of a bus cycle. When RDYD is not active, wait states are inserted by the device to accommodate slower memory or I/O devlces.
R/W
Read or write
M/IO
Memory or I/O
STRBA
Address strobe
RDYA
Address ready
STRBD
Data strobe
RDYD
Data ready
INFORMATION BUS Mnemonic IB0 - IB15 Name Information bus Description A bidirectional time-multiplexed address/data bus that is three-state during bus cycles not assigned to the CPU. IB0 is the most significant bit.
STATUS BUS Mnemonic AK0 - AK3 Name Access key Description Outputs used to match the access lock in the MMU for memory accesses (a mismatch will cause the MMU to pull the MEM PRT ER signal LOW), and also indicates processor state (PS). Privileged instructions can be executed with PS = 0 only. These signals are three-state during bus cycles not assigned to the CPU. Outputs that select the page register group in the MMU. It is three-state during bus cycles not assigned to the CPU. These outputs together with D/I can be used to expand the device direct addressing space to 4 MBytes, in a nonprotected mode (no MMU). However, using this addressing mode may produce situations not specified in MIL-STD-1750.
AS0 - AS3
Address state
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PACE1750AE
SIGNAL DESCRIPTIONS (Continued)
BUS ARBITRATION Mnemonic BUS REQ Name Bus request Description An active LOW output that indicates the CPU requires the bus. It becomes inactive when the CPU has acquired the bus and started the bus cycle. An active LOW input from an external arbiter that indicates the CPU currently has the highest priority bus request. If the bus is not used and not locked, the CPU may begin a bus cycle, commencing with the next CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), threestating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA, STRBD), and all the other lines that go three-state when this CPU does not have the bus. An active LOW, bidirectional signal used to establish the beginning and end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used for sampling bits into the fault register. It is three-state in bus cycles not assigned to this CPU. However, the CPU monitors the BUS BUSY line for latching non-CPU bus cycle faults into the fault register. An active low, bi-directional signal used to lock the bus for successive bus cycles. During non-locked bus cycles, the BUS LOCK signal mimics the BUS BUSY signal. It is three-state during bus cycles not assigned to the CPU. The following instructions will lock the bus: INCM, DECM, SB, RB, TSB, SRM, STUB and STLB.
BUS GNT
Bus grant
BUS BUSY
Bus busy
BUS LOCK
Bus lock
DISCRETE CONTROL Mnemonic DMA EN Name Direct memory Access enable Normal power up Description An active HIGH output that indicates the DMA is enabled. It is disabled when the CPU is initialized (reset) and can be enabled or disabled under program control (I/O commands DMAE, DMAD). An active HIGH output that is set when the CPU has successfully completed the built-in self test in the initialization sequence. It can be reset by the I/O command RNS. An active HIGH output that indicates a new instruction is about to start executing in the next cycle. An active LOW discrete output. This signal can be pulsed low under program control I/O address 400B (Hex) and is automatically pulsed during processor initialization.
NML PWRUP
SNEW TRIGO RST
Start new Trigger-go reset
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PACE1750AE
TERMINAL CONNECTIONS
Case Outline: Pin Grid Array (Case Z) Terminal Number B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 L2 K2 L3 K3 L4 K4 Terminal Symbol VCC IB14 IB13 IB12 IB11 IB10 IB9 IB8 GND IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 GND UNRCV ER TIMER CLK NML PWRUP RESET TRIGO RST Terminal Number L5 K5 L6 K6 L7 K7 L8 K8 L9 K9 L10 K11 K10 J11 J10 H11 H10 G11 G10 F11 F10 E11 E10 Terminal Symbol DMA EN CON REQ VCC SNEW BUS LOCK BUS GNT BUS BUSY M/IO D/I R/W GND RDYD RDYA BUS REQ STRBD STRBA CPU CLK AK0 AK1 AK2 AK3 GND AS0 Terminal Number D11 D10 C11 C10 B11 A10 B10 A9 B9 A8 B8 A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 Terminal Symbol AS1 AS2 AS3 IOL2INT VCC GND IOL1INT USR5INT USR4INT USR3INT USR2INT USR1INT USR0INT PWRDN INT GND MAJ ER SYSFLT1 SYSFLT0 EXT ADR ER MEM PAR ER MEM PRT ER IB15
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PACE1750AE
TERMINAL CONNECTIONS
Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with GullWing Leads (Case Y) Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Terminal Symbol GND CON REQ DMA EN TRIGO RST RESET NML PWRUP TIMER CLK UNRCV ER GND IB0 IB1 IB2 IB3 IB4 IB5 IB6 IB7 GND IB8 IB9 VCC IB10 Terminal Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Terminal Symbol IB11 IB12 IB13 IB14 IB15 MEM PRT ER MEM PAR ER EXT ADR ER SYSFLT0 SYSFLT1 MAJ ER GND VCC PWRDN INT USR0INT USR1INT USR2INT USR3INT USR4INT USR5INT IOL1INT IOL2INT AS3 Terminal Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Terminal Symbol AS2 AS1 AS0 GND AK3 AK2 VCC AK1 AK0 CPU CLK STRBA STRBD BUS REQ RDYA RDYD R/W D/I M/IO BUS BUSY BUS GNT BUS LOCK SNEW VCC
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PACE1750AE
TERMINAL CONNECTIONS
Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Terminal Symbol GND CON REQ DMA EN TRIGO RST RESET NML PWRUP TIMER CLK UNRCV ER IB0 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 IB9 VCC IB10 IB11 IB12 Terminal Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Terminal Symbol IB13 IB14 IB15 MEM PRT ER MEM PAR ER EXT ADR ER SYSFLT0 SYSFLT1 MAJ ER GND PWRDN INT USR0INT USR1INT USR2INT USR3INT USR4INT USR5INT IOL1INT IOL2INT AS3 AS2 Terminal Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Terminal Symbol AS1 AS0 GND AK3 AK2 AK1 AK0 CPU CLK STRBA STRBD BUS REQ RDYA RDYD R/W D/I M/IO BUS BUSY BUS GNT BUS LOCK SNEW VCC
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PACE1750AE
ORDERING INFORMATION
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PACE1750AE
CASE OUTLINE X:
64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C)
Inches .002 .005 .008 .010 .015 .016 .018 .025 .040 .050 .185 .265 .470 .530 .590 .620 .645 1.550 1.563 mm 0.05 0.12 0.20 0.25 0.38 0.40 0.45 0.63 1.01 1.27 4.70 6.73 11.93 13.46 14.98 15.74 16.38 39.37 39.70
NOTES:
1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
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PACE1750AE
CASE OUTLINE T:
64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G)
Inches .001 .003 .005 .008 .010 .015 .016 .022 .030 .040 .050 .150 .470 .530 .590 .620 .868 1.663 mm 0.03 0.08 0.12 0.20 0.25 0.38 0.41 0.55 0.76 1.01 1.27 3.81 11.93 13.46 14.98 15.74 22.04 42.24
NOTES:
1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration.
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PACE1750AE
CASE OUTLINE U:
68 Lead Quad Pack with Straight Leads (Ordering Code QL)
Inches .002 .004 .006 .010 .012 .020 .050 .100 .116 .250 .560 .570 .800 .955 1.090
mm 0.05 0.10 0.15 0.25 0.30 0.51 1.27 2.54 2.95 6.40 14.22 14.48 20.32 24.25 27.69
NOTES:
1) 2) 3) 4) 5) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched may be either notched or square.
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PACE1750AE
CASE OUTLINE Y:
68 Lead Quad Pack with Gullwing Leads (Ordering Code QG)
Inches .004 .005 .008 .010 .012 .015 .016 .020 .024 .040 .050 .100 .115 .570 .800 .955 1.010 1.090
mm 0.10 0.12 0.20 0.25 0.30 0.38 0.41 0.50 0.60 1.02 1.27 2.54 2.92 14.48 20.32 24.25 25.65 27.68
NOTES:
1) 2) 3) 4) 5) 6) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched my be either notched or square (with radius). Case Y is derived from Case U by forming the leads to the shown gullwing configuration.
Document # MICRO-2 REV G
Page 23 of 25
PACE1750AE
CASE OUTLINE Z:
68-Pin Pin Grid Array (PGA) (Ordering Code PG)
Inches .016 .020 .040 .050 .059 .060 .098 .100 .120 .150 .170 1.010 1.089 1.160
mm 0.41 0.50 1.01 1.27 1.49 1.52 2.49 2.54 3.04 3.81 4.32 25.65 27.66 29.46
NOTES:
1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid.
Document # MICRO-2 REV G
Page 24 of 25
PACE1750AE
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. ORIG A B C ISSUE DATE May-89 Jun-04 Jan-05 Feb-05 MICRO-2 PACE1750AE CMOS 16-BIT PROCESSOR ORIG. OF CHANGE RKK JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Added Pyramid logo Added 20 MHz speed Added thermal data (page 3), top brazed package drawing (page 19), and corrected errors on page 2. Added clarification to page 3, corrected Terminal Connections (pages 16-18) Removed 35 MHz device. Redrew timing diagrams and corrected the following symbols in the signal propagation delay table: 1) t(SDR)HIDX to tSDRH(IBD)X 2) tFC(IBA)V to tFC(IBA)X Altered case outline drawing for case X and case T
D
Mar-05
DAB
E F
Apr-05 Aug-05
JDB JDB
G
Oct-05
JDB
Document # MICRO-2 REV G
Page 25 of 25

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